Printed circuit board

ABSTRACT

A printed circuit board includes a base layer, a first conductive pattern, and a first surface treatment patterned layer formed on a portion of a surface of the first conductive pattern. The first conductive pattern includes a first copper foil layer on one side of the base layer and a first conductive layer on a portion of a surface of the first copper foil layer. The first conductive pattern which is covered by the first surface treatment patterned layer has sidewalls obliquely tilted with respect to the base layer. The first conductive pattern covered with the first surface treatment patterned layer has a cross section that is trapezoidal shaped, and a width which gradually decreases from the base layer to the first conductive layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional application of patent application Ser. No.14/848,517, filed on Sep. 9, 2015, assigned to the same assignee, whichis based on and claims priority to Chinese Patent Application number201510279753.5 filed on May 27, 2015, the contents of which areincorporated by reference herein.

FIELD

The subject matter herein generally relates to a printed circuit board.

BACKGROUND

In the field of printed circuit boards, the circuit board generallyincludes plating wires to electroplate the surface treatment layers forthe bonding pads after forming the solder mask layer. The plated wiresare extended from the bonding pads to the edge of the printed circuitboard and are covered by the solder mask layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations of the present technology will now be described, by wayof example only, with reference to the attached figures.

FIG. 1 is a cross sectional view of a substrate according to oneembodiment of the present disclosure.

FIG. 2 is a cross sectional view of substrate in FIG. 1 after drilling athrough hole.

FIG. 3 is a cross sectional view of a substrate in FIG. 2 after forminga seed layer on the surfaces of the copper foil layers and the wall ofthe through hole.

FIG. 4 is a cross sectional view of substrate in FIG. 3 after formingthe first and second patterned resist layers on part of the surface ofthe seed layer.

FIG. 5 is a cross sectional view of substrate in FIG. 4 after formingthe first and second conductive layers on part of the surface of theseed layer without removing the first and second patterned resistlayers.

FIG. 6 is a cross sectional view of substrate in FIG. 5 after formingthe third and fourth patterned resist layers on the surfaces of thefirst and second patterned resist layers and part of the surfaces of thefirst and second conductive layers.

FIG. 7 is a cross sectional view of substrate in FIG. 6 after formingthe first and second surface treatment patterned layers on the exposedsurfaces of the first and second conductive layers.

FIG. 8 is a cross sectional view of substrate in FIG. 7 after removingthe first, second, third, and fourth patterned resist layers.

FIG. 9 is a cross sectional view of substrate in FIG. 8 after etchingpart of the first and second conductive layers without covering thefirst and second surface treatment patterned layers, the exposed seedlayers, and the first and second copper foil layers under the exposedseed layers.

FIG. 10 is a cross sectional view of substrate in FIG. 9 after formingthe first solder mask layer and the second solder mask layer on thesurfaces of the first and second conductive layers which are not coveredwith the first and second surface treatment patterned layers and on partof the surfaces of the first and second surface treatment patternedlayers.

DETAILED DESCRIPTION OF EMBODIMENTS

It will be appreciated that for simplicity and clarity of illustration,where appropriate, reference numerals have been repeated among thedifferent figures to indicate corresponding or analogous elements. Inaddition, numerous specific details are set forth in order to provide athorough understanding of the embodiments described herein. However, itwill be understood by those of ordinary skill in the art that theembodiments described herein may be practiced without these specificdetails. In other instances, methods, procedures, and components havenot been described in detail so as not to obscure the related relevantfeature being described. Also, the description is not to be consideredas limiting the scope of the embodiments described herein. The drawingsare not necessarily to scale and the proportions of certain parts may beexaggerated to better illustrate details and features of the presentdisclosure.

The term “comprising,” when utilized, means “including, but notnecessarily limited to”; it specifically indicates open-ended inclusionor membership in the so-described combination, group, series, and thelike.

FIG. 1 to FIG. 10 illustrate a method of making a printed circuit board10.

FIGS. 1 to 10 are presented in accordance with an example embodiment.The one or more examples shown in FIGS. 1 to 10 is provided by way ofexample, as there are a variety of ways to carry out the method. Themethod described below can be carried out using the configurationsillustrated in FIGS. 1 to 10, for example, and various elements of thesefigures are referenced in explaining example method. Each of FIGS. 1 to10 represents one or more processes, methods or subroutines, carried outin the example method. Furthermore, the illustrated order of FIGS. 1 to10 is illustrative only and the order of FIGS. 1 to 10 can change.Additional processes can be added or fewer processes may be utilized,without departing from this disclosure.

FIG. 1 illustrates a substrate 11 including a base layer 110, a firstcopper foil layer 111 positioned on one side of the base layer 110, anda second copper foil layer 112 opposite to the first copper foil layer111 and positioned on other side of the base layer 110.

The base layer 110 can be a flexible resin layer, such as polyimide(PI), polyethylene terephthalate (PET), or polyethylene naphthalate(PEN). In other embodiments, the base layer 110 can be a multilayerflexible substrate, including the alternative multiple conductive resinlayers and multiple wiring layers. The first copper foil layer 111 andthe second copper foil layer 112 have a uniform thickness. The thicknessof the first copper foil layer 111 is the same as the thickness of thesecond copper foil layer 112 in at least one embodiment.

FIG. 2 illustrates a through hole 113 formed on the substrate 11 by amechanical drilling method or a laser ablation method. The through hole113 penetrates through the first copper foil layer 111, the base layer110, and the second foil layer 112.

FIG. 3 illustrates a seed layer 120 formed on the surfaces of the firstcopper foil layer 111 and the second copper foil layer 112 The seedlayer 120 is also formed on the wall of the through hole 113.

The seed layer 120 can be formed by a black hole process, a shadowprocess, or an electroless plating process. In at least one embodiment,the seed layer 120 is formed by electroless copper plating. In otherembodiments, the seed layer 120 can be omitted or formed only on thewall of the through hole 113.

FIG. 4 and FIG. 5 illustrate a first patterned resist layer 121 and asecond patterned resist layer 122 respectively formed on the surfaces ofthe seed layers 120 located on the first copper foil layer 111 and thesecond copper foil layer 112. A first conductive layer 131 is thenformed by electroplating surface of the seed layer 120 which is exposedfrom the first patterned resist layer 121 and positioned on the surfaceof the first copper foil layer 111 A second conductive layer 132 is alsoformed by electroplating on surface of the seed layer 120 which isexposed from the second patterned resist layer 122 and positioned on thesurface of the second copper foil layer 112. A third conductive layer130 is also formed by electroplating on the surface of the seed layer120 which is positioned on the wall of the through hole 113. Afterplating the third conductive layer 130, the through hole 113 with thethird conductive layer 130 becomes a conductive through layer 1131. Theconductive through hole 1131 electrically connects the first conductivelayer 131 and the second conductive layer 132. In at least oneembodiment, the first patterned resist layer 121 and the secondpatterned resist layer 122 can be dry film.

Both of the first conductive layer 131 and the second conductive layer132 have a uniform thickness. The thicknesses of the first conductivelayer 131 and the second conductive layer 132 are the same and aregreater than the thicknesses of the first copper foil layer 111 and thesecond copper foil layer 112. In addition, the thickness of the firstconductive layer 131 is greater than the sum of the thicknesses of thefirst copper foil layer 111 and the seed layer 120.

All of the seed layer 120, the first copper foil layer 111, and thesecond copper foil layer 112 which are not covered by the firstconductive layer 131, and the second conductive layer 132, are formed asa removable plating wire 114, to electrically connect the firstconductive layer 131 and the second conductive layer 132.

FIG. 6 and FIG. 7 illustrate a third patterned resist layer 123 formedon the surface of the first conductive layer 131 and the first patternedresist layer 121. The third patterned resist layer 123 covers the fullsurface of first patterned resist layer 121 and covers part of thesurface of the first conductive layer 131. In addition, a fourthpatterned resist layer 124 is formed on the surfaces of the secondconductive layer 132 and the second patterned resist layer 122. Thefourth patterned resist layer 124 covers the full surface of the secondpatterned resist layer 122 and covers part of the surface of the secondconductive layer 132. And then, the first conductive layer 131 which isexposed from the third patterned resist layer 123 and the secondconductive layer 132 which is exposed from the fourth patterned resistlayer 124 receive a surface treatment process. After the surfacetreatment process, a first surface treatment patterned layer 133 isformed on the exposed surface of the first conductive layer 131 and asecond surface treatment patterned layer 134 is formed on the exposedsurface of the second conductive layer 132 for protecting respectivelythe first conductive layer 131 and the second conductive layer 132. Thefirst surface treatment patterned layer 133 and the second surfacetreatment patterned layer 134 can be made of a nickel-gold (Ni—Au)layer, a nickel-platinum-gold (Ni—Pt—Au) layer, or anickel-palladium-gold (Ni—Pd—Au) layer. As mentioned above, theremovable plating wire 114 including all of the seed layer 120, thefirst copper foil layer 111, and the second copper foil layer 112 whichare not covered by the first conductive layer 131 or by the secondconductive layer 132 is used to electrically connect the firstconductive layer 131 and the second conductive layer 132. The removableplating wire 114 is used for respectively electroplating the firstsurface treatment patterned layer 133 and the second surface treatmentpatterned layer 134 on the surfaces of the first conductive layer 131and the second conductive layer 132 during the surface treatmentprocess. In at least one embodiment, the removable plating wire 114mentioned above is used as the plating wire for electroplating thesurface treatment patterned layers.

FIG. 8 and FIG. 9 illustrate that the first patterned resist layer 121,the second patterned resist layer 122, the third patterned resist layer123, and the fourth patterned resist layer 124 are removed. Afterremoving the patterned resist layers, each of the seed layer 120, thefirst copper foil layer 111, and the second copper foil layer 112 whichare exposed from the first conductive layer 131 or from the secondconductive layer 132 are etched. And then, a first conductive pattern135 and a second conductive pattern 136 are formed on the differentsides of the base layer 110.

In at least one embodiment, the first surface treatment patterned layer133 and the second surface treatment patterned layer 134 arerespectively used as mask layers for etching the first conductive layer131 and the second conductive layer 132. The first conductive layer 131and the second conductive layer 132 are used as mask layers for etchingthe seed layer 120. The seed layer 120 which is exposed from the firstconductive layer 131 or from the second conductive layer 132 is removedby etching. In addition, the first copper foil layer 111 and the secondcopper foil layer 112 under the exposed seed layer 120 are also removedby etching in the same process. Since all of the seed layer 120, thefirst copper foil layer 111, and the second copper foil layer 112 whichare exposed from the first conductive layer 131 or from the secondconductive layer 132 are etched, it means that the removable platingwire 114 can be removed by etching without any residual wire extendingto the end of the substrate 11.

The first conductive layer 131 and the second conductive layer 132 whichare not covered with the first surface treatment patterned layer 133 andthe second surface treatment patterned layer 134 are exposed to theetching solution and are also etched to reduce the thicknesses. Asmentioned above, the first conductive layer 131 and the secondconductive layer 132 both have a uniform thickness. The thicknesses ofeach of the first conductive layer 131 and the second conductive layer132 are the same and such thickness is greater than the thicknesses ofthe first copper foil layer 111 and the second copper foil layer 112. Inaddition, the thickness of the first conductive layer 131 is greaterthan the sum of the thicknesses of the first copper foil layer 111 andthe seed layer 120. Therefore, when removing by etching the seed layer120, the first copper foil layer 111, and the second copper foil layer112 which are not covered with either the first conductive layer 131 orthe second conductive layer 132, the first conductive layer 131 and thesecond conductive layer 132 which are not covered with either the firstsurface treatment patterned layer 133 or the second surface treatmentpatterned layer 134 are also etched to reduce the thicknesses. Afteretching, the first conductive pattern 135 is formed by the first copperfoil layer 111, the seed layer 120 on the first copper foil layer 111,and the first conductive layer 131 on the seed layer 120. In addition,the second conductive pattern 136 is formed by the second copper foillayer 112, the seed layer 120 on the second copper foil layer 112, andthe second conductive layer 132 on the seed layer 120. The firstconductive pattern 135 and the second conductive pattern 136 areelectrically connected by the conductive through hole 1131.

In the present embodiment, the thickness of the first conductive pattern135 which is covered with the first surface treatment patterned layer133 is greater than the thickness of the first conductive pattern 135which is not covered with the first surface treatment patterned layer133. In addition, the thickness of the second conductive pattern 136which is covered with the second surface treatment patterned layer 134is greater than the thickness of the second conductive pattern 136 whichis not covered with the second surface treatment patterned layer 134.

In this disclosure, the different layers of different thicknesses andcharacteristics result in different etching rates. The side walls of thefirst conductive pattern 135 and the second conductive pattern 136 in atleast one embodiment are not perpendicular to the base layer 110 and areobliquely tilted with respect to the base layer 110. Therefore, thecross section of the first conductive pattern 135 and the secondconductive pattern 136 is a trapezoidal shape. The width of the firstconductive pattern 135 is decreased from the base layer 110 to the firstsurface treatment patterned layer 133. In addition, the width of thesecond conductive pattern 136 is decreased from the base layer 110 tothe second surface treatment patterned layer 134.

FIG. 10 illustrates a first solder mask layer 141 and a second soldermask layer 142 formed on the surfaces of the first conductive pattern135 and the second conductive pattern 136. Thereby, a printed circuitboard 10 is obtained.

In at least one embodiment, the first solder mask layer 141 covers thesurface of the first conductive pattern 135 which is exposed from thefirst surface treatment patterned layer 133, and covers a portion of thesurfaces of the first surface treatment patterned layer 133 and the baselayer 110 at the same side. The portion of the first surface treatmentpatterned layer 133 which is exposed from the first solder mask layer141 is used as a first connective portion 151. The first connectiveportion 151 includes a first bonding pad 1511 and a first conductivefinger 1512. In the same process, the second solder mask layer 142covers the surface of the second conductive pattern 136 which is exposedfrom the second surface treatment patterned layer 134 and covers aportion of the surfaces of the second surface treatment patterned layer134 and the base layer 110 at the same side. The portion of the secondsurface treatment patterned layer 134 which is exposed from the secondsolder mask layer 142 is used as a second connective portion 152. Thesecond connective portion 152 includes a second bonding pad 1521 and asecond conductive finger 1522.

In this disclosure, the removable plating wire 114 is removed by etchingbefore forming the solder mask layer and without any residual wireneeding to be extended to the edge of the substrate 11. Theelectroplating process is used for plating the first surface treatmentpatterned layer 133 and the second surface treatment patterned layer 134by using the removable plating wire 114. The electroplating process issimplified by using the removable plating wire 114 instead of thetraditional plating wires. The electroplating process eliminates thetraditional plated wires under the solder mask layer for plating thefirst surface treatment patterned layer 133 and the second surfacetreatment patterned layers 134 and effectively reduces noise in signaltransmission and makes finer pitch design in the circuit.

It can be understood that the method of manufacturing a printed circuitboard 10 further includes the steps to remove the waste parts.

A printed circuit board 10 is also disclosed. The printed circuit board10 includes a substrate 11 comprising a base layer 110, a firstconductive pattern 135 formed on one side of the base layer 110, and asecond conductive pattern 136 which is opposite to the first conductivepattern 135 and formed on another side of the base layer 110. Thesubstrate 11 also includes a first surface treatment patterned layer 133formed on part of the surface of the first conductive pattern 135, and asecond surface treatment patterned layer 134 formed on part of thesurface of the second conductive pattern 136. The substrate 11 furthercomprises a first solder mask layer 141 formed on part of the surface ofthe first surface treatment patterned layer 133 and the first conductivepattern 135, and a second solder mask layer 142 formed on part of thesurface of the second surface treatment patterned layer 134 and thesecond conductive pattern 136.

In at least one embodiment, the first solder mask layer 141 covers thesurface of the first conductive pattern 135 which is exposed from thefirst surface treatment patterned layer 133 Certain parts of thesurfaces of the first surface treatment patterned layer 133 and the baselayer 110 at the same side are also covered by the first solder masklayer 141. The portion of the first surface treatment patterned layer133 exposed from the first solder mask layer 141 is used as a firstconnective portion 151. The second solder mask layer 142 covers thesurface of the second conductive pattern 136 which is exposed from thesecond surface treatment patterned layer 134 and covers part of thesurfaces of the second surface treatment patterned layer 134 and thebase layer 110 at the same side. The portion of the second surfacetreatment patterned layer 134 which is exposed from the second soldermask layer 142 is used as a second connective portion 152. The printedcircuit board 10 further includes at least one through hole 113.

The printed circuit board 10 further includes a first copper foil layer111 positioned on a surface of the base layer 110, and a second copperfoil layer 112 opposite to the first copper foil layer 111.

The printed circuit board 10 further includes a first conductive layer131 positioned on the surface of the first copper foil layer 111, asecond conductive layer 132 positioned on the surface of the second foillayer 112, and a third conductive layer 130 positioned on the wall ofthe through hole 113. The through hole 113 thus becomes a conductivethrough hole 1131. The conductive through hole 1131 electricallyconnects with the first conductive pattern 135 and the second conductivepattern 136.

The printed circuit board 10 further includes a seed layer 120 formed onthe surface of the first copper foil layer 111, the surface of thesecond copper foil layer 112, and the wall of the conductive throughhole 1131. The seed layer 120 formed on the surface of first copper foillayer 111 is positioned between the first copper foil layer 111 and thefirst conductive layer 131. In addition, the seed layer 120 formed onthe surface of second copper foil layer 112 is positioned between thesecond copper foil layer 112 and the second conductive layer 132. In theillustrated embodiment, the seed layer 120 is positioned under the firstconductive layer 131, the second conductive layer 132, and the thirdconductive layer 133.

The first conductive pattern 135 of the printed circuit board 10 can bemade by at least one of the first copper foil layer 111, the secondcopper foil layer 112, the seed layer 120, the first conductive layer131, and the second conductive layer 132.

The substrate 11 may include a plurality of units for forming aplurality of printed circuit boards 10. After the first solder masklayer 141 and the second solder mask layer 142 are formed on thesubstrate 11, the substrate 11 can be cut to form a plurality ofseparate printed circuits boards 10.

The method of manufacturing a printed circuit board 10 in presentdisclosure is to form a conductive layer by electroplating on thesurfaces of the first copper foil layer 111 and the second copper foillayer 112. The conductive layer includes the first conductive layer 131,the second conductive layer 132, and the third conductive layer 130.Until the first copper foil layer 111 and the second copper foil layer112 are etched, the first copper foil layer 111 and the second copperfoil layer 112 are continuous layers. After electroplating theconductive layer and forming the conductive through hole 1131, theentire substrate 11 is electrically conductive. All of the first copperfoil layer 111, the second copper foil layer 112, and the seed layer 120not covered by either the first conductive layer 131 or the secondconductive layer 132 can be used as a removable plating wire 114 toelectroplate the first surface treatment patterned layer 133 and thesecond surface treatment patterned layer 134 on the conductive layer.Using the removable plating wire 114 avoids the residual plated wireshaving adverse effects on signal transmission and ensures the electricalquality of the printed circuit board. In this disclosure, no additionalplated wires are required and the space for the wiring design isincreased to allow finer pitch design. In addition, the conductive layerformed by the electroplating has better non-scratch properties.

The embodiments shown and described above are only examples. Manydetails are often found in the art such as the other features of aprinted circuit board. Therefore, many such details are neither shownnor described. Even though numerous characteristics and advantages ofthe present technology have been set forth in the foregoing description,together with details of the structure and function of the presentdisclosure, the disclosure is illustrative only, and changes may be madein the detail, especially in matters of shape, size, and arrangement ofthe parts within the principles of the present disclosure, up to andincluding the full extent established by the broad general meaning ofthe terms used in the claims. It will therefore be appreciated that theembodiments described above may be modified within the scope of theclaims.

What is claimed is:
 1. A printed circuit board comprising: a base layer;a first conductive pattern comprising: a first copper foil layer formedon one side of the base layer; and a first conductive layer formed on aportion of a surface of the first copper foil layer; and a first surfacetreatment patterned layer formed on a portion of a surface of the firstconductive pattern, wherein the first conductive pattern which iscovered with the first surface treatment patterned layer has sidewallstilted with respect to the base layer at an oblique angle, the firstconductive pattern covered with the first surface treatment patternedlayer having a cross section that is trapezoidal shaped, and a widthgradually decreasing in a direction from the base layer to the firstconductive layer.
 2. The printed circuit board of claim 1, wherein athickness of the first conductive layer is greater than a thickness ofthe first copper foil layer.
 3. The printed circuit board of claim 1,wherein a thickness of the first conductive pattern covered with thefirst surface treatment patterned layer is greater than a thickness ofthe first conductive pattern that is not covered with the first surfacetreatment patterned layer.
 4. The printed circuit board of claim 1,wherein the first surface treatment patterned layer is made ofnickel-gold (Ni—Au), nickel-platinum-gold (Ni—Pt—Au), ornickel-palladium-gold (Ni—Pd—Au).
 5. The printed circuit board of claim1, wherein the printed circuit board further comprises a first soldermask layer, the first solder mask layer covers the surface of the firstconductive pattern, which is not covered with the first surfacetreatment patterned layer, and part of the surfaces of the first surfacetreatment patterned layer and the base layer at the same side, and thefirst surface treatment patterned layer exposed from the first soldermask layer becomes a first connective portion.
 6. The printed circuitboard of claim 5, wherein the first connective portion is a bonding pador a conductive finger.
 7. The printed circuit board of claim 1, whereinthe printed circuit board further comprises: a second conductive patternformed on another side of the base layer, and the second conductivepattern is opposite to the first conductive pattern, the secondconductive pattern comprises: a second copper foil layer, the secondcopper foil layer is opposite to the first copper foil layer; and asecond conductive layer formed on a portion of a surface of the secondfoil layer; and a second surface treatment patterned layer formed on aportion of a surface of the second conductive pattern; and a throughhole covered with a third conductive layer to be formed as a conductivethrough hole for connecting the first conductive pattern and the secondconductive pattern, wherein the second conductive pattern which iscovered with the second surface treatment patterned layer has sidewallstilted with respect to the base layer at an oblique angle, the secondconductive pattern covered with the second surface treatment patternedlayer having a cross section that is trapezoidal shaped, and a widthgradually decreased in a direction from the base layer to the secondconductive layer.
 8. The printed circuit board of claim 7, wherein athickness of the second conductive pattern which is covered with thesecond surface treatment patterned layer is greater than a thickness ofthe second conductive pattern which is not covered with the secondsurface treatment patterned layer.
 9. The printed circuit board of claim7, wherein the printed circuit board further comprises a seed layer, theseed layer is positioned on the surfaces of the first copper foil layer,the second copper foil layer, and on the wall of the through hole, andthe seed layer is positioned under the first conductive layer, thesecond conductive layer, and the third conductive layer.
 10. The printedcircuit board of claim 9, wherein a thickness of the second conductivelayer is greater than a sum of thicknesses of the second copper foillayer and the seed layer positioned on the second copper foil layer.